I work on software that needs to know the processor and cache details. On x86 systems it uses the CPUID instruction to know about the processor family/model (Skylake, Icelake etc) and cache details (total size, line size, associativity etc). I am trying to do the same on ARM systems. I am using RedHat Linux. I noticed that the dmidecode command has an entry called ID.
dmidecode reads the SMBIOS files, The SMBIOS spec says that the value of ID is taken from the MIDR_EL1 register of ARM. So, can the value of ID be used to distinguish between different ARM processors e.g eMAG1 and eMAg2?
dmidecode also gives cache details (with “-t cache”) but only total size and associativity. Cache line size is not given. Is there an instruction or register that can be used to get all the details?
The ARMv8 spec mentions a register called CTR_EL0. It has the following field
DminLine, bits [19:16]
Log2 of the number of words in the smallest cache line of all the data caches and unified caches that
are controlled by the PE.
This seems to only give the smallest possible line size. I am interested in the actual line size (and other details) of the caches.
1. What is Ampere eMAG core ID and how do I found out?
For MIDR definition, see ARMv8.x specification. eMAG 1st generation has
the MIDR_EL1 as 0x503F000Y where Y is the chip revision. The Implementer
for eMAG 1st generation is 0x50. (Please note that future generation chip
will have the Implementer as 0xC0.) The Variant is 0x3F. Architecture is 0xF.
PartNum is 0. The Revision depends on the chip revision.
The core ID can be determined by reading the MIDR_EL1 or via the SMBIOS table
using the application program dmidecode. Because the way firmware works, the endianness
may be reversed. The SMBIOS shows the below information:
ID: 50 3F 00 02 00 00 00 00
2. How to determine the eMAG core cache size?
The eMAG cache size of L1, L2, L3 or system level cache can only be determined
from the SMBIOS table via dmidecode.