Home Community Getting Started Processor ID

This topic contains 2 replies, has 2 voices, and was last updated by  Karthikeyan Karthikeyan 1 year, 5 months ago.

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  • #758

    I have access to a few Ampere systems at work. I was checking the processor data in the SMBIOS and noticed two different ID values

    00 00 00 00 01 00 3F 50
    00 00 00 00 02 00 3F 50

    I have two questions :

    1). Do these refer to eMAG 1st Gen and eMAG 2nd Gen OR do they just refer to two different versions of eMAG 1st gen?

    2). The SMBIOS spec says that the processor ID data is from the contents of the MIDR_EL register.
    According to the ARM v8 spec, bits[31:24] must contain the implementer’s code, which is given
    as 0xC0 for Ampere. But there is no 0xC0 in the ID values, given above, Instead bits[31:24]
    contain 0x1 and 0x2. Why?


  • #759

    Mauri Whalen

    Karthikeyan –

    My apologies for the delay, we had a small glitch in our email system.

    eMAG FAQ

    1. What is Ampere eMAG core ID and how do I found out?

    For MIDR definition, see ARMv8.x specification. eMAG 1st generation has
    the MIDR_EL1 as 0x503F000Y where Y is the chip revision. The Implementer
    for eMAG 1st generation is 0x50. (Please note that future generation chip
    will have the Implementer as 0xC0.) The Variant is 0x3F. Architecture is 0xF.
    PartNum is 0. The Revision depends on the chip revision.

    For example:

    0x503F0001 represents eMAG rev Ax
    0x503F0002 represents eMAG rev B0

    The core ID can be determined by reading the MIDR_EL1 or via the SMBIOS table
    using the application program dmidecode. Because the way firmware works, the endianness
    may be reversed. The SMBIOS shows the below information:

    ID: 50 3F 00 02 00 00 00 00

    2. How to determine the eMAG core cache size?

    The eMAG cache size of L1, L2, L3 or system level cache can only be determined
    from the SMBIOS table via dmidecode.

    Mauri Whalen
    Ampere Computing

  • #763

    Thanks Mauri.

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